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Publications of Author

Journal papers
[10] K. Le, D. Declercq, F. Ghaffari, L. Kessal, O. Boncalo and V. Savin, "Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes", in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, pp. 2183-2195, July 2018.
[9] K. Le, F. Ghaffari, L. Kessal, D. Declercq, E. Boutillon, C. Winstead, B. Vasic. "A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes", IEEE Transactions on Circuits and Systems I: Regular Papers, jan 2018, pp. 1 - 14.
[8] L. Bendaouia, L. Kessal, S. M. Karabernou, H. Salhi, F. Ykhlef New Design Approach of FIR Filters Based-FPGA-Implementation for a Bio-Inspired Medical Hearing Aid. International Journal of Advances in Systems and Measurments Vol. 6 Number 1 & 2, 2013.
[7] L. Gantel, A. Khiar, B. Miramond, M. E. A. Benkhelifa, L. Kessal, F. Lemonnier, J. Le Rhun, Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications, ACM transactions on Reconfigurable Technology and Systems (TRETS) 5, 3, 2012.
[6] S. Khatchadourian, J.C. Prevotet, and L. Kessal, Hardware Architecture for Pattern Recognition in Gamma-ray Experiment. EURASIP Journal on Embedded Systems, 2009.
[5] L. Kessal, N. Abel, S. M. Karabernou, and D. Demigny, Reconfigurable Computing: Design Methodology and Hardware Tasks Scheduling for Real-Time Image Processing. Journal of Real-Time Image Processing, number 3, volume 3, pp.131-147, 2008.
[4] L. Kessal, N. Abel, et D. Demigny, Traitement temps réel des images en exploitant la reconfiguration dynamique : architecture et programmation, Traitement du signal, number 1, volume 3, pp.41-58, 2006.
[3] L. Kessal, N. Abel, and D. Demigny, Real-time Image Processing With Dynamically Recongurable Architecture, Real Time Imaging, Elsevier, 9 pp.297-313, 2003.
[2] D. Demigny, F. Garcia Lorca, et L. Kessal, De l'Architecture à l'algorithme ? un exemple : le détecteur de contours de Deriche, Traitement du signal Numéro Spécial Adéquation Algorithme Architecture, 14(6) pp.615-623, november 1997.
[1] D. Demigny, J. Devars, L. Kessal, et J.F. Quesne, Implantation temps réel du filtre de lissage d'images de Nagao, Traitement du signal, 10(4) pp.319-330, 1993.

International Conferences
[19] F. Cochachin, D. Declercq, E. Boutillon, L. Kessal Density evolution thresholds for noise-against-noise min-sum decoders 2017 IEEE 28th Annual International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), Oct 2017, Montreal.
[18] K. Le, F. Ghaffari, L. Kessal, D. Declercq, V. Savin and O. Boncalo “Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes”, accepted in Circuits and Systems (ISCAS 2018), IEEE International Symposium on, Italy, 27-30, May 2018.
[17] L. Bendaouia, H. Salhi, S. M. Karabernou, L. Kessal, DWT based Implementation of a Reconfigurable Platform for Medical Hearing Aid, in International conference on Communication and Signal Processing (MIC-SMD2012), Turquie, 2012.
[16] L. Bendaouia, S. M. Karabernou, L. Kessal, H. Salhi, F. Ykhlef, New Design Approach of an FIR Filters Based FPGA-implementation for a Bio-Inspired Medical Hearing Aid, in The Fifth International Conference on Advances in Circuits, Electronics and Micro-electronics, IARA, CENICS 2012, Italie, 2012.
[15] L. Bendaouia, S. M. Karabernou, L. Kessal, Fast DWT Based FPGA Implementation for Medical Application, in 8th International Conference On Wearable Micro and Nano Technologies for Personalised Health (pHealth'11), France, 2011.
[14] L. Gantel, A. Khiar, B. Miramond, M. A. Benkhelifa, F. Lemonnier, L. Kessal, Dataflow Programming Model For Reconfigurable Computing, in 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'11). Montpellier, France, 2011.
[13] R. Narayanan, S. Khatchadourian, J. C. Prevotet, L. Kessal, Neural network hardware architecture for pattern recognition in the HESS2 project, in ESANN 2008 proceedings, Bruges, Belgium, 2008.
[12] S. Khatchadourian, J. C. Prevotet, and L. Kessal, Efficient Level 2 Trigger System Based on Artificial Neural Networks, in XII International Workshop on Advanced Computing and Analysis Techniques in Physics Research (ACAT'08), Italy, 2008.
[11] S. Khatchadourian, J. C. Prevotet, and L. Kessal, A Neural Solution for the Level 2 Trigger in Gamma Ray Astronomy, in XI Advanced Computing and Analysis Techniques in Physics Research (ACAT'07), Amsterdam, the Netherlands, 2007.
[10] N. Abel, L. Kessal, S. Pillement, and D. Demigny, Clear stream towards dynamically reconfigurable systems on chip, in 2nd European Workshop on Reconfigurable Communication-centric SoCs (ReCoSoC'06). Montpellier, France, 2006.
[9] N. Abel, L. Kessal, et D. Demigny, Design flexibility using FPGA dynamical reconfiguration, in ICIP 2004, Singapour, October 2004.
[8] P. Lamaty, B. Mazar, D. Demigny, L. Kessal, et Si M. Karabernou, Two ASIC for low and middle levels of real time image processing, in 11th IFIP International Conference on Very Large Scale Integration, number 1, pages 87-92, Montpellier, France, 2001.
[7] L. Kessal, R. Bourguiba, D. Demigny, N. Boudouani, et Si M. Karabernou, Reconfigurable architecture using high speed FPGA, in 11th IFIP International Conference on Very Large Scale Integration, number 1, pages 261-268, Montpellier, France, 2001.
[6] D. Demigny, L. Kessal, et J. Pons, Fast recursive implementation of the Gaussian filter, in 11th IFIP International Conference on Very Large Scale Integration, number 1, pages 339-346, Montpellier, France, 2001.
[5] L. Kessal, D. Demigny, N. Boudouani, et R. Bourguiba, Reconfigurable hardware for real time image processing, in Proc. International Conference on Image Processing (IEEE ICIP), volume 3, pages 159-173, Vancouver, 2000.
[4] D. Demigny, L. Kessal, R. Bourguiba, et N. Boudouani, How to use high speed reconfigurable FPGA for real time image processing ?, in IEEE Conf. on Computer Architecture for Machine Perception (IEEE Circuit and Systems), pages 240-246, Padova, 2000.
[3] R. Bourguiba, D. Demigny, et L. Kessal, Dynamic configuration : a new paradigm applied to real time image analysis, in The tenth International Conference on Microelectronics (IEEE Electron Devices Society), pages 25-28, Tunisia, 1998.
[2] R. Bourguiba, D. Demigny, Si M. Karabernou, et L. Kessal, Designing a new architecture for real time image analysis with dinamically configurable FPGAs, in IEEE - IMACS Computational Engineering in Systems Applications (IEEE Systems Man and Cybernetics), pages 739-743, 1998.
[1] F. G. Lorca, L. Kessal, and D. Demigny, Efficient asic and fpga implementations of iir filters for real time edge detection, in International Conference on Image Processing (IEEE ICIP), number 2, pages 406-409, Santa Barbara, 1997.

Book chapters
[4] P. Lamaty, B. Mazar, D. Demigny, L. Kessal, et M. Karabernou, System on chip methodologies, chapter Two ASIC for low and middle levels of real time image processing, pp. 3-14 , in Kluwer, Edited by M. Robert, B. Rouzeyre, C. Piguet and M. L. Flottes, 2002.
[3] D. Demigny, L. Kessal, et J. Pons, System on chip methodologies, chapter Fast recursive implementation of the Gaussian filter, pp. 39-50 , in Kluwer, Edited by M. Robert, B. Rouzeyre, C. Piguet and M. L. Flottes, 2002.
[2] L. Kessal, R. Bourguiba, D. Demigny, N. Boudouani, et M. Karabernou, System on chip methodologies, chapter Reconfigurable architecture using high speed FPGA, pp. 75-86 , in Kluwer, Edited by M. Robert, B. Rouzeyre, C. Piguet and M. L. Flottes, 2002.
[1] L. Kessal, Méthodes et architectures pour le TSI en temps réel, Traité Information, Commande et Communication, chapitre 7, Conception pour DSP SHARC, pages 143-168, , in Hermès (D. Demigny coordonateur), 2001.

National publications
[16] L. Kessal, Contributions à la conception d'architectures à reconfiguration dynamique pour le traitement temps réel des images, Habilitation à diriger des recherches (in french), Université de Cergy Pontoise, 15 décembre 2004.
[15] L. Kessal, Simulation, mise en oeuvre et tests logiciels et matériels d'un processeur expérimental orienté traitement symbolique : PEARLS, PhD dissersation (in french), Université de Paris-Sud, 27 mars 1987.
[14] S. Khatchadourian, R. Narayanan, J.C. Prévotet, and L. Kessal, Architecture matérielle pour implantation de réseaux de neurones en temps réel, 22ème colloque GRETSI, Dijon, septembre 2009.
[13] L. Kessal, N. Abel, et D. Demigny, Développement des IPs et ordonnancement des configurations dans une Architecture à Reconfiguration Dynamique, JFAAA'5, Dijon (France), 18-21 janvier 2005.
[12] N. Abel, L. Kessal, et D. Demigny, Mise en oeuvre du lisseur de Deriche sur l'architecture reconfigurable dynamiquement ARDOISE, Titre, In Telecom Paris, éditeur, GRETSI, volume I, pages 376-379, Paris (France), Septembre 2003.
[11] N. Abel, D. Demigny, L. Kessal, et N. Boudouani, Mise en oeuvre de la reconfiguration partielle sur l'architecture reconfigurable ARDOISE, In Proceedings of the JFAAA, pages 45-48, Monastir, Tunisie, Dec. 2002.
[10] D. Demigny, N. Boudouani, N. Abel, et L. Kessal, La rémanence des architectures reconfigurables : un critère significatif de classification des architectures, In Proceedings of the JFAAA, pages 49-52, Monastir, Tunisie, Dec. 2002.
[9] N. Boudouani, D. Demigny, et L. Kessal, Evaluation d'un algorithme de détection de mouvement par approche markovienne sur composants reconfigurables dynamiquement, In 18 ème Colloque sur le traitement de images et du signal (GRETSI), Toulouse, septembre 2001.
[8] D. Demigny, J. Pons, N. Boudouani, et L. Kessal, Réalisation récursive temps réel de filtre RIF : filtre de Canny, filtre gaussien et ses dérivées, In 18 ème Colloque sur le traitement de images et du signal (GRETSI), Toulouse, septembre 2001.
[7] L. Kessal, D. Demigny, R. Bourguiba, et N. Boudouani, Architecture reconfigurable : méthodologie et outils de développement, In 6ème Symposium en architectures nouvelles de machines, pages 110-113, Besançon, juin 2000.
[6] P. Lamaty, D. Demigny, L. Kessal, et Si M. Karabernou, Système intégrétemps réel pour l'analyse d'images, In 18 ème Colloque imagerie rapide et photonique (DGA,SFO,CNRS ISIS,CRITT), Arcueil, mai 2000.
[5] D. Demigny, N. Boudouani, R. Bourguiba, et L. Kessal, Vers une méthodologie pour la programmation des architectures à reconfiguration dynamique, In Actes du workshop Adéquation Algorithmes Architectures En Traitement Du Signal et de L'image (CNRS, GDR ISIS, INRIA), pages 15-20, Rocquencourt, janvier 2000.
[4] R. Bourguiba, D. Demigny, et L. Kessal, Architecture reconfigurable dynamiquement, application au traitement d'images, In Actes des Journées Thématiques Universités/Industries sur l'Adéquation Algorithme-Architecture pour les Applications Temps Réel Industrielles Complexes (GRAISyHM, GDR-PRC ISIS), pages 80-87, Lille, Mars 1999.
[3] R. Bourguiba, L. Kessal, et D. Demigny, Reconfiguration Dynamique des FPGA pour une segmentation d'image adaptative et temps réel, In 16 ème Colloque sur le traitement de images et du signal (GRETSI), number 1, pages 591-594, Grenoble, septembre 1997.
[2] D. Demigny, L. Kessal, F. Garcia Lorca, et J.P. Cocquerez, Conceptions nouvelles du détecteur de contours de Deriche, In Actes des Journées Adéquation Algorithmes Architectures En Traitement Du Signal et de L'image (CNRS, GDR ISIS, CNES), pages 45-52, Toulouse, janvier 1996.
[1] D. Demigny, L. Kessal, T. Kamlé, et J.P. Cocquerez, Filtre de Deriche, Architectures Temps Réel pour la segmentation Multi-Résolution, In 14 ème Colloque sur le traitement des images et du signal (GRETSI), number 2, pages 1035-1038, Juan Les Pins, septembre 1993.




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