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Short Bio

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I received a Master Degree in Computer Science and Telecommunication from University of Poitiers specialized in Real-time System and Embedded Multimedia in 2011, after acheiving a Computer Science Degree from University of Sciences and Technology HOUARI BOUMEDIENE in 2010, specialized in Computer, Information and Network Security. Since October 2011, I am a PhD student at ETIS Laboratory - UMR 8051 CNRS/ENSEA/University of Cergy-Pontoise - working on reliability of reconfigurable Architectures and Real-Time Systems with Bertrand Granado, Fakhreddine Ghaffari and Amine Benkhelifa.

  • My research interests include Field-Programmable Gate Arrays (FPGAs) with emphasis on :
  • Dependability & Reliability.
  • Online Fault Mitigation Methods.
  • Real-Time & Reconfigurable Architectures.
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    Vitae

    • 2011-Current : PhD Thesis
    • Laboratory : ETIS (ASTRE Team).
      Topics : Toward new Real-time operating system providing reliability for dynamically reconfigurable systems.
      Advisors: Bertrand Granado, Fakhreddine Ghaffari & Amine Benkhelifa.

    • 2010-2011 : Master of Science
    • M.Sc. : Master IT in Real-time System and Embedded Multimedia, University of Poitier, France.

    • 2005-2010 : Bachelor of Science
    • Engineer : from University of Sciences and Technology HOUARI BOUMEDIENE, Algeria.
      Specialization : Computer, Information and Network Security

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    Teaching

    • IUT of Cergy-Pontoise [2011-2014] :
    • Real-Time programming in ┬ÁC/OS-II system on Xilinx FPGAs (Labs).
      Industrial Assembly/C programming for 8051 MCU (Labs).

    • ENSEA [2014-2015]:
    • Fundamentals Assembly/C Programming for ARM Cortex-M3 Processor (STM32) (Labs).
      Analog-to-digital (ADC)& digital-to-analog (DAC) with ARM Cortex-M3 Processor (STM32) (Labs).

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    Publications

    Context-Aware Resources Placement for SRAM-based FPGA to minimize Checkpoint/Recovery overhead,
    F. Sahraoui, F. Ghaffari, M. E. A. Benkhelifa, B. Granado

    2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), DOI.

    Reliability Assessment of Backward Error Recovery for SRAM-based FPGAs,
    F. Sahraoui, F. Ghaffari, M. E. A. Benkhelifa, B. Granado

    9th International Design and Test Symposium (IDT), 2014, DOI.

    Fast SRAM-FPGA Fault Injection Platform based On Dynamic Partial Reconfiguration,
    F. Ghaffari, F. Sahraoui, M. E. A. Benkhelifa, B. Granado, M. A. Kacou, O. Romain

    26th International Conference on Microelectronics (ICM), 2014, DOI.

    An Injection Fault Flow based On Module Isolation for Reliability Evaluation of SRAM-FPGA,
    F. Sahraoui, F. Ghaffari, M. E. A. Benkhelifa, B. Granado

    in 8th National GdR System on Chip - System in Package (SoC-SiP), 2014.

    An Efficient BER-based Reliability Method For SRAM-based FPGA,
    F. Sahraoui, F. Ghaffari, M. E. A. Benkhelifa, B. Granado

    International Design and Test Symposium (IDT), 2013 8th , DOI.

    Backward Error Recovery for SRAM-Based FPGAs,
    F. Sahraoui, F. Ghaffari, M. E. A. Benkhelifa, B. Granado

    in 7th National GdR System on Chip - System in Package (SoC-SiP), 2013.

    Enhanced Error-Correcting Code with Checkpoint/Recovery on FPGAs,
    F. Sahraoui, F. Ghaffari, M. E. A. Benkhelifa, B. Granado

    in 6th National GdR System on Chip - System in Package (SoC-SiP), 2012.

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    Contact Information

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    ETIS Laboratory

    6, avenue du Ponceau
    95014 CERGY PONTOISE CEDEX
    France

    Phone: 0033-130-736-285
    Email: fouad.sahraoui{at}ensea.fr
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